Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains comprising multiple scan cells. The scan cells may be implemented, by way of example, utilizing respective flip-flops. The scan cells of a given scan chain are configurable to form a serial shift register for applying test patterns at inputs to combinational logic of the integrated circuit. The scan cells of the given scan chain are also used to capture outputs from other combinational logic of the integrated circuit.
Scan testing of an integrated circuit may therefore be viewed as being performed in two repeating phases, namely, a scan shift phase in which the flip-flops of the scan chain are configured as a serial shift register for shifting in and shifting out of test patterns, and a scan capture phase in which the flip-flops of the scan chain capture combinational logic outputs. These two repeating scan test phases may be collectively referred to herein as a scan test mode of operation of the integrated circuit, or as simply a scan mode of operation.
Outside of the scan test mode and its scan shift and capture phases, the integrated circuit may be said to be in a functional mode of operation. Other definitions of the scan test and functional operating modes may also be used. For example, the capture phase associated with a given scan test may instead be considered part of a functional mode of operation, such that the modes include a scan shift mode having only the scan shift phase, and a functional mode that includes the capture phase.
Integrated circuits commonly include multiple clock domains. In an integrated circuit of this type, different portions of the integrated circuit are provided with different clock signals via a clock distribution network. For scan testing purposes, several clock signals having a common frequency but associated with different clock domains may be synchronized with one another. This is often done to facilitate scan testing. However, in some situations this type of simplification can be problematic, in that clock delay defects detected for synchronized clock signals during scan testing may nonetheless permit proper functional operation of the integrated circuit, because the functional operation may not require these clock signals to be synchronous. This can reduce device yield when manufacturing integrated circuits, as the devices failing the scan testing may be rejected for clock delay defects that do not actually interfere with functional operation.